By JosA© T. de Sousa, Peter Y.K. Cheung
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Extra info for Boundary-Scan Interconnect Diagnosis (Frontiers in Electronic Testing)
Memory chips are a good example of this (de Jong and van Wijngaarden, 1992). INTRODUCTION 13 Nonetheless, the general tendency is that the use of glue logic declines for various reasons: (1) full BS design requirement (2) rapid development of interface protocols, and (3) use of reconfigurable computing technology. , 1990). In regard to reason (2), an example is the use of the peripheral component interconnect (PCI) standard; this standard has greatly reduced the need for glue logic interfaces (Michel, 1994).
If the circuit passes this test it is deemed fault free. Otherwise, based on the response of the first test set, a few additional test vectors are computed on the fly and applied to the circuit. These additional vectors are supposed to diagnose the fault in question. , 1990). Two-step diagnosis seems attractive at first, but has some severe problems. First of all, compared to single-step strategies, where a single test set is applied, 12 Boundary-Scan Interconnect Diagnosis adaptive T&D is slower.
The random approach is a kind of Monte Carlo simulation where defects with a random size are randomly scattered over the layout. This Boundary-Scan Interconnect Diagnosiss 18 approach makes sense for ICs where defects of random size and location can occur in the layout. It also gives some measure of the occurrence probability of defects. However, large numbers of defects have to be generated in order to study an adequate number of possible faulty situations and their probabilities. This limits the size of the circuits that can be analyzed.